A behavioral modeling methodology which enables full chip mixed-signal simulation of a new PRML (Partial Response Maximum Likelihood) disk drive read/write IC is described. Three levels of model abstraction are developed which range from high level used in system definition to implementation specific based on individual circuit behaviour. Models are written in a combination of the MAST modeling language, Verilog, and Fortran. Descriptions of the sub-systems that comprise the chip and modeling techniques are given followed by a comparison of behavioral simulation to actual lab data from the fabricated device.
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