VLSI architecture for discrete wavelet transform based on B-spline factorization

摘要

Based on B-spline factorization, a new category of architectures for the discrete wavelet transform (DWT) is proposed. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of a Pascal implementation. The latter is the only part requiring multipliers and can be implemented with type-I or type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could need fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with small area and low speed because only a few adders are on the critical path. Two cases of the JPEG2000 defaulted (9,7) filter and the (6,10) filter are given to demonstrate the efficiency of the proposed architectures.