Real-time speech synthesis on an ultra low-resource, programmable DSP system

摘要

An efficient implementation of a time-domain speech synthesis system on an ultra low-power, miniature, programmable block-floating-point DSP system is introduced. The DSP system, operating at a clock rate as low as 1.28 MHz, is well suited for speech and audio processing applications. Similar to the MBR-PSOLA technique, this time-domain synthesis method uses a normalized speech database generated by a high-quality harmonic synthesis. To reduce the memory usage and communication bandwidth, the normalized database is compressed using a block-adaptive, ADPCM approach. Listening tests, comparing the synthetic speech quality on the DSP system and the same method implemented on a high-resource computer system, show no degradations due to the memory, register length, or other low-resource limitations on the DSP system. The system consumes less than 1 mW at 1 volt.