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On designing mixed-signal programmable fuzzy logic controllers as embedded subsystems in standard CMOS technologies

机译:在将混合信号可编程模糊逻辑控制器设计为标准CMOS技术中的嵌入式子系统时

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A digitally-programmable analogue fuzzy logic controller (FLC) is presented. Input and output signals are processed in the analog domain whereas the parameters of the controller are stored in a built-in digital memory. Some new functional blocks have been designed whereas others were improved towards the optimisation of the power consumption, the speed and the modularity while keeping a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4/spl mu/ technology, showing good agreement with the expected performances, namely: from 2.22 to 5.26 Mflips (mega fuzzy logic inferences per second) at the pin terminals (@CL= 13pF), 933 /spl mu/W power consumption per rule (@Vdd=5V) and 5 bits of resolution. Since the circuit is intended for a subsystem embedded in an application chip (@CL/spl les/5pF) up to 8 Mflips may be expected.
机译:提出了一种数字可编程模拟模糊逻辑控制器(FLC)。输入和输出信号在模拟域中进行处理,而控制器的参数则存储在内置数字存储器中。设计了一些新的功能块,而对其他一些功能块进行了改进,以优化功耗,速度和模块性,同时保持合理的精度,这是一些模拟信号处理应用程序所需要的。使用标准的CMOS 2.4 / spl mu /技术制造了一个九规则,两输入一输出的原型,并成功进行了测试,表明与预期的性能有很好的一致性,即:从2.22到5.26 Mflips(每兆兆模糊逻辑推论)秒)在引脚端子(@ CL = 13pF),每规则933 / spl mu / W功耗(@ Vdd = 5V)和5位分辨率。由于该电路用于嵌入在应用芯片中的子系统(@ CL / spl les / 5pF),因此最高可望达到8 Mflips。

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