Speculations about the ability of asynchronous systems to take advantage of the data dependent performance of circuit components have been widespread. Simulations and actual designs have not however provided much confirmation that it is possible to transfer the average case data dependent performance of a single stage into average case performance of a system without paying an unacceptable area penalty in the implementation. Here it is shown that if area*time is chosen as the performance metric to be minimized there are in fact absolute theoretical limits to achieving data dependent performance as compared with synchronous circuits. These limits are shown to arise in two completely different theoretical approaches each of which make few assumptions about the distribution of data dependent delays experienced when the circuit operates. The theoretical approach confirms many of the tradeoffs that designers of data dependent circuits have long suspected.
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