An H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed and flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and memory control. The other portion of the H.263 video codec and other parts of the H.324 system like G.723, H.223, and H.245 are implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an architecture for a hierarchical motion estimator using correlation of neighboring motion vectors is suggested to reduce the chip size. Software optimization techniques are also explored using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD) obtained from the motion estimator.
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