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A low-voltage CMOS rail-to-rail class-AB input/output opamp with slew-rate and settling enhancement

机译:具有压摆率和建立增强功能的低压CMOS轨至轨AB类输入/输出运算放大器

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A low-voltage CMOS rail-to-rail op amp with high slew-rate and fast-settling is presented. The input stage is composed of the complementary differential pairs, a pair of modified current-mode maximum selecting circuits (Maximum Current Selecting Circuit II) and a class-AB feedback loop circuit. It achieves rail-to-rail operation, constant-g/sub m/, high slew-rate and fast-settling. With this opamp topology, the design can be easily performed for a wide-range of capacitive loads with a large bandwidth-to-power-consumption ratio. With 2 /spl mu/m and 0.5 /spl mu/m technology respectively, the op amp has a high DC gain (/spl ges/84 dB), and has a bandwidth-to-power-consumption ratio of 13.6 MHz/mW and 25.8 MHz/mW with capacitive loads of 20 pF, 86 V//spl mu/s, S0 V//spl mu/s slew-rate and 159 ns, 36 ns settling-time.
机译:提出了一种具有高摆率和快速建立的低压CMOS轨到轨运算放大器。输入级由互补差分对,一对修改的电流模式最大选择电路(最大电流选择电路II)和AB类反馈环路电路组成。它实现了轨到轨操作,恒定g / sub m /,高摆率和快速沉降。借助这种运算放大器拓扑,可以轻松地针对具有大带宽功耗比的各种电容性负载进行设计。分别采用2 / spl mu / m和0.5 / spl mu / m技术,该运算放大器具有很高的DC增益(/ spl ges / 84 dB),带宽/功耗比为13.6 MHz / mW电容负载为20 pF,86 V // splμs/ s,S0 V // splμ/ s摆率和159 ns,36 ns的建立时间时,频率为25.8 MHz / mW。

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