A 100 kHz 9.6 mW multi bit /spl Delta//spl Sigma/ DAC and ADC using noise shaping dynamic elements matching with tree structure

摘要

A multi-bit /spl Delta//spl Sigma/ modulator (/spl Delta//spl Sigma/M) is an attractive means for realizing a high-speed low-power data converter. A loss in dynamic range occurs if stabilization of the feedback loop for a higher-order DSM uses a 1b feedback signal. The classical 1b ADC and/or DAC do not follow the theoretical SNR of (8+6 N)L(dB), where N is the order of the DSM, and 2/sup L/ is the oversampling ratio. In contrast, multi-bit feedback stabilizes a higher-order DSM with little loss of dynamic range. As the internal signal swing is reduced with increase in number of feedback signal bits, the multi-bit DSM requires a lower slew rate and thus less power for analog circuits than the 1b case. There is an increase in SNR due to use of a multi-bit internal DAC to reduce the oversampling ratio and hence to reduce power consumption of the analog portion.