Cache coherence and synchronization between processors have been two critical issues in designing a shared memory multiprocessors system. From the perspective of hardware design, a directory based cache coherence protocol and lock mechanism are employed to prevent inconsistency of caches and warrant atomic memory accesses. The BY91-1 multiprocessors efficiently integrate supports for cache coherence and hardware based primitives by using a uniform directory scheme which is dubbed as Dir/sub 2/NB+L. This integration allows for low hardware overhead while maintaining both a coherent caches system and indivisible memory accesses in a scalable and cohesive fashion. This paper describes the design and rationale of this versatile directory scheme. Results on the evaluation of different directory schemes based on a preliminary simulator-CASIMU demonstrate that Dir/sub 2/NB+L scheme is cost-effective. We also report on the experience gained by implementing this directory scheme on BY91-1 multiprocessors system. We believe that this scheme is well suited for CC-NUMA architecture.
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机译：高速缓存的一致性和处理器之间的同步已成为设计共享内存多处理器系统中的两个关键问题。从硬件设计的角度来看，采用了基于目录的缓存一致性协议和锁定机制来防止缓存不一致并保证原子内存访问。 BY91-1多处理器通过使用称为Dir / sub 2 / NB + L的统一目录方案，有效地集成了对缓存一致性和基于硬件的基元的支持。这种集成允许较低的硬件开销，同时以可伸缩和紧密结合的方式维持一致的缓存系统和不可分割的内存访问。本文介绍了这种通用目录方案的设计和原理。基于初步的模拟器CASIMU对不同目录方案进行评估的结果表明，Dir / sub 2 / NB + L方案具有成本效益。我们还将报告在BY91-1多处理器系统上实施此目录方案所获得的经验。我们认为该方案非常适合CC-NUMA体系结构。
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