Statistical correction of A/D converter errors

摘要

A method to correct the pipelined and multi-step A/D converter errors is proposed and implemented on a low-power 12-bit 10 M sample/s analog-to-digital converter. The converter consumes 315 mW from a single 5 V supply and exhibits wide input bandwidth, good linearity (DNL=-0.36 LSB), and low distortion with a spurious-free dynamic range (SFDR) of 83 dB.