Accelerating CFD applications by improving cached data reuse

摘要

As processors continue to experience relatively rapid clock speed increases, the gap widens between cpu and memory performance. Unlike other studies that collect memory traces and analyze them for compile time optimization or propose cache organization best suited for an application group, this paper tackles the problem at its roots, namely analyzing data access patterns and optimizing them before implementation. Optimization done by today's compilers is mostly loop level. Function level optimization is limited to inlining code that often leads to poor instruction cache utilization, affecting code performance adversely. In this study, an algorithm to solve compressible Euler equations is studied with regard to temporal and spatial access of data. Data and instruction blocks, which are used most often, are isolated. The algorithm is then coded to utilize the characteristics of hierarchical memories with as much as 45% improvement over conventional optimization techniques.