A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries

摘要

The design of low-cost mixed/mode VLSI systems requires compact power-efficient library cells with a good performance. Digital library cells fully benefit from the continuing down-scaling of CMOS processes, since these cells contain minimum-size components. Analog library cells, such as the op amp, cannot be designed using minimum-size transistors, for reasons of gain, offset, etc. Moreover, low-voltage rail-to-rail requirements complicate the design. To obtain compact low-voltage analog cells with a good performance, simple power-efficient designs need to be developed. This paper presents a compact two-stage 3 V CMOS opamp that is suitable as a VLSI library cell because of its small die area.