Summary form only given. We describe a methodology for integrating plasma technology into large wafer manufacturing processes for the purpose of controlling the critical dimensions of those wafers. The Plasma Assisted Chemical Etching (PACE) process is now used commercially to control the Total Thickness variation (TTV) of bulk silicon wafers to /spl les/0.2 /spl mu/m and to produce bonded Silicon-on-Insulator (SOI) wafers with active layers having mean thicknesses of 100-nm or less and layer thickness variations well under 10-nm. We will review recent data supporting the ability of the PACE process to achieve this dimensional control on 200-mm bulk Si and bonded SOI wafers.
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机译:仅提供摘要表格。我们描述了一种将等离子技术集成到大型晶圆制造工艺中的方法,以控制这些晶圆的关键尺寸。等离子辅助化学蚀刻(PACE)工艺现已在商业上用于控制散装硅片的总厚度变化(TTV)到/ spl les / 0.2 / spl mu / m,并生产粘合绝缘体上硅(SOI)晶片有源层的平均厚度为100纳米或更小,且层厚度变化在10纳米以下。我们将回顾支持PACE工艺在200mm块状Si和键合SOI晶圆上实现此尺寸控制的能力的最新数据。
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