Arithmetic codec from behavioral description based LSI-CAD for fully programmable image coding system

摘要

Entropy coding, as used for lossless compression in image coding, is dominated by serial bit processing and recursive conditional branches. Digital signal processors (DSPs), in which pipeline processors play a central role, fail to yield adequate performance for this kind of application. This paper focuses on arithmetic coding in order to design a high speed and fully programmable entropy codec using a high-level behavioral description based LSI-CAD system. The design of the arithmetic encoder and decoder with the hardware description language is detailed as well as the simulations performed on this design. The results concerning the logic synthesis show that this approach attains complete success for practical applications and ensures flexible hardware design involving relatively complicated functions within reasonable time and cost requirements.