The authors present a scalable ATM switch architecture which features output queuing with no internal speedup. The architecture takes advantage of the knockout principle to obtain tradeoff between the hardware complexity and the cell loss probability. Components of the switch include a Batcher sorter, an address resolution module, a banyan network, and output buffers. The hardware complexity of the switch, O(LNlog(LN)) where L is the number of cells allowed into an output queue in a single time slot and N is the number of ports, is comparable to the input queuing Batcher-banyan switch (O(Nlog/sup 2/N)), but performance is consistent with other more complex output queuing architectures.
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