Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved schemes, skewed schemes and XOR schemes. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.
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