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Reliability analysis of a fault-tolerant multi-bus multiprocessor system

机译:容错多总线多处理器系统的可靠性分析

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The paper proposes a fault-tolerant multi-bus system called binomial multi-bus architecture and analyses its reliability using a combinatorial method involving unreliability and mutually exclusive partitioning. Some attractive features of this architecture include low interconnection complexity, and a high degree of fault-tolerance. It is found that the probability of bus survival has a greater influence on the system reliability than the processors or memory modules. Comparison with the fully connected multi-bus architecture shows an important result, i.e. at least one-third of the connection cost is reduced at the expense of only a very slight decrease in the system reliability. Thus, the proposed architecture exhibits a strong potential to be a cost-effective interconnection network.
机译:本文提出了一种称为二项式多总线体系结构的容错多总线系统,并使用涉及不可靠性和互斥分区的组合方法来分析其可靠性。该体系结构的一些吸引人的功能包括低互连复杂度和高度的容错能力。发现总线生存的可能性比处理器或内存模块对系统可靠性的影响更大。与完全连接的多总线体系结构进行比较显示了一个重要的结果,即减少了至少三分之一的连接成本,但代价是仅略微降低了系统可靠性。因此,所提出的架构展现出成为具有成本效益的互连网络的强大潜力。

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