A systolic array implementation of a general-purpose inference processor is presented. The proposed processor can be used as a building block in the inference engine of an expert system or in a rule-based controller where computational speed is of importance. After a brief theoretical review of the approximate-reasoning, a VLSI implementation exploiting the parallelism in that routine is presented. The paper concludes with a discussion of programmability and other problems related to the practical application of the proposed processors.
展开▼