An interprocessor communication strategy for the application of clock-skewed parallel processing (CSPP) to fine-grain DSP systems is proposed. The strategy is a combination of a synchronous multiprocessor architecture, an associated interprocessor communication architecture, and a multiprocessor compiler which considers the interprocessor communication to be a scheduling constraint. The resulting synchronous multiprocessor implementations are realized deterministically without a semaphore mechanism, and are also rate-optimal and processor-optimal.
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