An improved desynchronizer with reduced waiting time jitter for digital TDM systems

摘要

A new desynchronizer (or clock recovery circuit) for reducing waiting time jitter in TDM systems is described. The initial results indicate that this new method of clock recovery can give a significant reduction (approximately 50% for most DS-1 frequency offsets) in both the peak-to-peak and the r.m.s. waiting time jitter, as compared to the method currently used. With optimization of the system, further improvement should be possible.