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An efficient approach to test verification for VLSI circuits

机译:一种有效的VLSI电路测试验证方法

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A novel fault-detection scheme, called DRC (delay redundancy check), is proposed. This scheme is designed to be combined with VRC and HRC (vertical and horizontal redundancy check) to achieve a high fault coverage. The minimum distance is increased by two, and delay elements are used to skew the outputs in time. The lost fault coverage of the test verification scheme VRC+HRC+DRC is calculated as one out of 2/sup 5n-8/*m/sup 4/ for an n-input and m-output CUT (circuit under test). Using the two-signature approach for the data compaction of the output sequences of VRC+HRC and DRC, the frequency of fault masking is reduced to one in 2/sup 4n/ for an n-input and m-output CUT, where 2/sup n/
机译:提出了一种新颖的故障检测方案,称为DRC(延迟冗余检查)。该方案旨在与VRC和HRC(垂直和水平冗余校验)结合使用,以实现较高的故障覆盖率。最小距离增加了两倍,并且使用了延迟元件来使输出及时偏移。对于n输入和m输出CUT(被测电路),将测试验证方案VRC + HRC + DRC的丢失故障覆盖率计算为2 / sup 5n-8 / * m / sup 4 /之一。使用双签名方法对VRC + HRC和DRC的输出序列进行数据压缩,对于n输入和m输出CUT,故障屏蔽的频率降低为2 / sup 4n /,其中2 / sup n / <米

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