An efficient and flexible bit-level systolic array for inner product computation

摘要

A bit-level bit-serial systolic array is proposed for inner product computation. If data vectors are entered continuously and interleavedly, the proposed inner product array can be fully utilized for one of two operating modes: (1) computing two independent inner products concurrently, or (2) computing the sum of two inner products or an inner product with a double size. For a given data word length B, the system yields two outputs every 2B cycles for mode 1, ie, the average throughput is one per B cycle, and one output every 2B cycles for mode 2. The feature makes the inner product array more flexible for use in applications as compared to existing related systems. FIR filters based on the array are described for demonstration of its flexibility.