An assembly source level global compacter for digital signal processors

摘要

A global compacter is presented for digital signal processors. The global compaction algorithm outlined demonstrates that optimal or near-optimal code can be produced for digital signal processing (DSP) chips by employing conventional compiler optimization techniques in conjunction with a global compacter and a loop pipeliner. Code can be efficiently compacted across basic block boundaries as well as within basic blocks. The loop pipeliner produces optimal or near-optimal pipelined loops for any looping structure. The global compacter can be used by both high-level-language compilers and hand assemblers.