It is shown that, by using simple circuit techniques and a few modifications to cache organization, one can effectively eliminate the refreshing requirement of a DRAM. A selective invalidation scheme is employed. Selective invalidation can be implemented with a small (six transistors per subblock) circuit. The performances of the DRAM cache with selective invalidation and an equivalent SRAM cache are compared. The difference in performance is quite small even for large caches using selective invalidation. By replacing the SRAM cache with higher-density DRAM, the area efficiency and overall processor performance can be greatly improved. The miss ratio difference in large caches indicates that there are some cache entries active at intervals greater than the refresh period. This may depend on the referencing behavior of program or data.
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