Design and analysis of a fault tolerant multiprocessor system with failsafe and failsafe-redundant interfacing schemes

摘要

The design issues and implementation of a fault-tolerant multiprocessor system are addressed. Two design alternatives, termed failsafe and failsafe-redundant, are presented. The modular software presented previously by the authors (1989) for a tri-module redundant (TMR) system is easily transportable to the proposed architecture. The results of a reliability analysis for the two design schemes are presented. The proposed arbitration schemes can be integrated in LSI for improved reliability.