首页> 外文会议>Joint 2015 e-Manufacturing amp; Design Collaboration Symposium 2015 and 2015 International Symposium on Semiconductor Manufacturing >Inspection sensitivity improvement by wafer sort failure sites matching algorithm — Chimin Chen
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Inspection sensitivity improvement by wafer sort failure sites matching algorithm — Chimin Chen

机译:通过晶圆分类失败部位匹配算法提高检测灵敏度—陈奇敏

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摘要

Micro-crack of ILD oxide in peripheral area leads to wafer sort leakage failure issue. However, high nuisance rate in peripheral area inspection cannot monitor it effectively. This paper addresses a new methodology to improve the inspection sensitivity by transferring the wafer sort specific failure sites into GDS coordinates on design layout. These failure sites are the patterns of interest (POIs) which induced micro-crack easily. Further patterns grouping and searching will find out the similar patterns in whole chip, therefore, we can transfer these POIs into thousands to millions of care areas to do the extreme high sensitivity inspection. As compared to previous full scan area, the care area reduction with small POIs clips is 1/10 of original full scan area. High sensitivity inspection can monitor critical processes effectively, and improve the turnaround time (TAT) of product development efficiently.
机译:ILD氧化物在外围区域的微裂纹会导致晶圆分类泄漏失败问题。但是,外围区域检查中的高干扰率无法对其进行有效监视。本文提出了一种通过将晶圆分类特定的故障部位转移到设计版图上的GDS坐标中来提高检查灵敏度的新方法。这些失效部位是容易引起微裂纹的目标模式(POI)。进一步的模式分组和搜索将在整个芯片中找到相似的模式,因此,我们可以将这些POI转移到数千到数百万个护理区域中,以进行极高的灵敏度检查。与以前的完整扫描区域相比,使用小POI片段减少的护理区域是原始完整扫描区域的1/10。高灵敏度检查可以有效地监视关键过程,并有效地缩短产品开发的周转时间(TAT)。

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