An Effective Path Delay Fault Test Generation Algorithm for Digital Circuit

摘要

An effective path delay fault test generation algorithm for digital circuit is proposed in this paper because of its importance. The digital circuit is transformed firstly a partial leaf-dag circuit using path-leaf transformation. Then we generate test vectors for stuck-at fault in the partial leaf-dag circuit using improved Boolean difference method. Finally we transform the test vectors into two-pattern tests vectors for path delay fault in the original digital circuit. The experimental results on some international standard circuits demonstrate the feasibility and the effectiveness of the algorithm.