Chipset for a Single-Board MPEG-2 SSP@H-1440L HDTV-Decoder

摘要

This paper presents the VLSI realization of an MPEG-2 conformant hierarchical video decoder based on the Spatially Scalable Profile at the High-1440 Level (SSP@H-14L). The decoder is built at the Heinrich-Hertz-Institut (HHI) as part of the ongoing joint R&D project "Hierarchical Digital Television Transmission" (~H(DTV)_T) and will be demonstrated during the international exhibition IFA 1995 in Berlin. The project proposes a compatible approch to HDTV (TV-HDTV compatibility due to spatial scalability). Terrestrial broadcasting with graceful degradation and portable reception (through spatial and SNR scalability) are supported besides the less demanding cable and satellite scenarios.