DRAC: Adaptive Control System with Hardware Performance Counters

摘要

The memory hierarchy becomes the bottleneck for multiprocessors systems as its evolution does not keep pace with processor technology. This study intends to identify the relationship between performance slow-down and memory pressure, using hardware performance counters. Based on this relationship, we propose an adaptive control system that improves the efficiency of load balancing among the computer resources. The DRAC system, our adaptive control system, observes the access requests on the memory bus. It then adapts its user-level scheduling strategy to maximize the resource utilization. We describe the DRAC system and its mathematical model. We show experimental results that prove the DRAC system is nearly optimal with our model.