Implementation of efficient modular bypass multiplier logic in RSA cryptographic processor

摘要

Data security is in high demand in day to day digital life, complex cryptographic structures need to be modified to address the need of security from smart phones to define computers. This work focuses on both speed and area concerning objective. Numerous control strategies are introduced in both Gate and CMOS level, Multipliers are the basic design unit of a reconfigurable cryptographic processor. As cryptography structure majorly depends on multiplier and modular units, this paper utilizes the advantage of Bypass multiplier with modified modular multiplier logic with reduces area over ahead more than 8% and speed optimization to 25%.