A Systolic Architecture for Frame-Level FSBM Motion Estimation and Compensation

摘要

Full-search block-matching (FSBM) is a preferred approach to motion estimation. Frame-level pipelined FSBM architectures have advantages over block-level pipelined architectures in simpler control and reduced memory accesses. A type of frame-level pipelined FSBM architectures has data flow in the processor array in such a way that motion estimation and motion compensation can be computed concurrently. This would speed up video compression. In this paper, we present a frame-level pipelined FSBM motion estimation array processor for search range p = N and an architecture capable of computing both motion estimation and motion compensation at the same time. The architecture capable of motion compensation is suitable for applications where the block size can be small.