Designing Reversible Memory

摘要

This paper presents the issues involved in designing a memory system which is reversible and therefore does not erase information during its operation. High level issues of how the memory is accessed are discussed, along with low level switching circuit implementation issues, all involving techniques to avoid information erasure. A number of reversible switching circuit topologies have been found. The paper concludes with a discussion of the XRAM chip, an eight word by eight bit reversible memory chip submitted for fabrication in a 0.5 mum CMOS process. This chip performs exchange operations rather than traditional read/write operations, and is implemented in a reversible, adiabatic logic family, SCRL.