A Self-Evolutionary Emulation Scheme for A Networking Oriented Data-Driven Processor Architecture: CUE

摘要

This paper presents the effectiveness of a self-evolutionary emulation scheme, which accurately elicits the characteristics of CUE processor. CUE processor is a networking oriented data-driven processor consisting of multiple rings of self-timed elastic pipelines. The performance of CUE processor is determined by the packet-flow rate in each pipeline, and hence knowing the accurate packet-flow is crucial in evaluating or designing the CUE processor. Since autonomous cyclic inter-stage communications based on handshaking dictates the pipeline stage level packet-flow, a parallel performance evaluation scheme at pipeline stage level requires a fine-grain event communication support. Accordingly, a self-evolutionary emulation scheme, developed on multiple CUE processors themselves to utilize their abundant fine-grain parallel processing capability, is proposed in this paper. This paper demonstrates (1) scalability with respect to the augmentation of emulation facility, (2) interactivity with regard to a practical size of target programs and (3) superiority to the tradirional discrete event simulation scheme with the latest von Neumann processor.