JBits Based Fault Tolerant Framework for Evolvable Hardware

摘要

This work proposes a framework using JBits for the detection, isolation and correction of single component permanent faults for evolved digital circuits. To start with, given the input/output sequences, multiple working designs of the digital circuit are evolved using genetic algorithms. Each of these solutions is documented with the used and unused resources information that will be helpful in fault isolation and correction. The evolved circuit in operation, is constantly monitored for faults either using a self-checking circuit or the TMR technique depending on the criticality of the application. Once a fault is detected, the fault isolator identifies the faulty path as well as the exact faulty component. Once the fault is identified, one of the multiple versions already evolved and not making use of the faulty component is downloaded to provide fault correction. Depending on the number of versions evolved, 100% single component fault correction can be achieved. The proposed fault tolerance framework has been tested for ISCAS'89 benchmark circuits.