A Scene Test Methodology for IP Core Based on Wishbone Bus Architecture

摘要

With the development of integrate circuit technology, IP core reuse becomes the mainstream in the field of SOC designs. Some researches on Wishbone bus architecture and some IP test methods are done which are widely applied in SOC designs of the world firstly, and a scene test methodology for IP core based on Wishbone bus architecture is then introduced in this article. The experimental results confirm that this test methodology can obviously reduce the difficulty of test and speed up the design on system-level. Also, the methodology can increase the efficiency of test excitations and observable circuit test coverage.