MAPPING TECHNIQUES TARGETING MINIMUM DELAY FOR K-LUT BASED FPGA EVALUATION

摘要

The field programmable gate-array appeared last decade of previous millennium as alternative to application-specific integrated circuit (ASIC) projects. Static random-access memory (SRAM) is dominant FPGA technology in which programmability is realized by using SRAM cells to implement both programmable logic blocks and control programmable routing resources. Basic reported algorithms and techniques used for mapping k-LUT based FPGAs circuits are summarized, compared and evaluated using only delays minimum criteria.