Design and Verification of I/O Controller for Future Communication System

摘要

In this paper, we design a PCI Express controller for future communication system. The controller supports full functionality of Transaction Layer and Data Link Layer of PCI Express. The designed controller has the proposed transmitter buffer, which merges the transmitting buffer and the replay buffer, to obey Replay mechanism. Because buffer can it can dynamically adjust size of a replay buffer space, it has the higher data transfer efficiency than conventional buffer architecture. We also design Transmitter Transaction Layer of the designed controller to effectively support the proposed buffer. We propose the simple receiver buffer scheme to easily support Flow Control. We employ 80C51 to manage the functional blocks of the designed controller. We also implement Real-Time OS, MicroC/OS II on 80C5I and code software to fully cover the PCI Express protocols. For verification, we define the assembler instructions to generate situations that it will occur in actual operation and build a test bench including functional models of Host Bridge, Local Master, and Local Slave.