Instruction Level Tampering Detection Technique using Error Detection Code for Embedded Systems

摘要

In this paper, we propose new novel method for detecting tampered instructions by software attacks or hardware attacks before their execution in embedded systems. We apply an error detection technique used in communication systems instead of cipher technique. This technique can perform same functionality such as conventional secure processor architectures which detect tampered instructions by cipher technique of instructions. Also, due to both hight complex computation of cipher process and low processing speed of cipher modules, conventional secure processor architectures applying cipher technique can incur serious performance degradation. While, our technique applying error detecting code does not cause excessive performance decrease by complexity of computation and speed of tampering detection modules. According to experimental results, average performance degradation and memory overhead are 1.6% and 28% respectively, which are acceptable results for the security measures of embedded systems.