A Hybrid Branch Prediction Scheme

摘要

Providing accurate branch prediction is critical to exploit instruction level parallelism effectively. Some of the existing branch prediction methods are static: compilers use opcode information and profiling statistics to make predictions. Other branch prediction methods are dynamic: hardware uses execution history collected at run-time to make predictions. In this paper, we propose a hybrid branch prediction scheme that combines hardware and software techniques to improve the branch prediction accuracy. This hybrid scheme integrates an improved static branch prediction and a new dynamic branch predictor. The dynamic branch predictor consists of a "Switch-Counter" in addition to a two-level adaptive branch predictor. Using trace-driven simulation on SPEC95 benchmarks, the results indicate that this scheme provides an improvement over the existing branch prediction methods at similar hardware cost.