On Cache Contention of Parallel Protocol Processing in SMT

摘要

High performance protocol processing plays more and more important role in current high speed network security. Recent studies show that current computer architecture advances and CPU performance improvement has limited impact on network protocol processing performance. Some researchers find that on real SMT processor like Intel Xeon processor with Hyper-Threadings, the sharing resources (like cache) contention between threads can hurt the performance of network processing applications like servers or IDS. In this paper, we put our focus on the processing performance of TCP automata phases, using execution based simulations to model the relation between each phase cache behavior and cache size, and then measuring the cache contention between threads.