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A VLSI Architecture Design of CAVLC Decoder

机译:CAVLC解码器的VLSI架构设计

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摘要

Variable length code is an integral component of many international standards on image and video compression/Recently, Context-based Adaptive Variable Length Coding (CAVLC) is adopted by the emerging JVT (also called H.264 in ITU, and AVC in MPEG-4). In this paper, we describe a novel architecture for CAVLC decoder, including a coeff_token decoder, level decoder, total_zeros decoder and run_before decoder. Together with a barrel shifter and controller, the pipeline architecture can decode every syntax element in one clock cycle. Therefore, it is very suitable for video applications that require high throughput.
机译:可变长度代码是许多有关图像和视频压缩的国际标准的组成部分/最近,新兴的JVT(在ITU中也称为H.264,在MPEG-4中也称为AVC)采用了基于上下文的自适应可变长度编码(CAVLC) )。在本文中,我们描述了一种用于CAVLC解码器的新颖体系结构,包括coeff_token解码器,级别解码器,total_zeros解码器和run_before解码器。流水线体系结构与桶形移位器和控制器一起,可以在一个时钟周期内解码每个语法元素。因此,它非常适合需要高吞吐量的视频应用。

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