首页> 外文会议>International Conference on ASIC; 20031021-20031024; Beijng; CN >A Parallel Architecture for VLSI Implementation of FFT Processor
【24h】

A Parallel Architecture for VLSI Implementation of FFT Processor

机译:FFT处理器VLSI实现的并行架构

获取原文
获取原文并翻译 | 示例

摘要

In this paper, we propose an implementation method with high throughput for a single-chip 4096 complex point FFT. In order to increase transform speed, a parallel FFT architecture has been used. There are eight parallel basic processing modules in the entire FFT chip, which can work at the same time independently. The proposed structure can compute 4096 complex point forward or inverse FFT in real time with up to 320MHZ sampling frequency, and will be applied widely in high-speed signal processing.
机译:在本文中,我们提出了一种针对单芯片4096个复点FFT的高吞吐量实现方法。为了提高变换速度,已经使用了并行FFT架构。整个FFT芯片中有八个并行的基本处理模块,它们可以同时独立工作。所提出的结构能够以高达320MHZ的采样频率实时计算4096个复点正向或反向FFT,并将广泛应用于高速信号处理中。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号