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Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic

机译:多单元表征:为快速单通量量子(RSFQ)逻辑开发健壮的单元和抽象

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RSFQ, a Josephson-junction based technology, is becoming attractive due to its low energy and high speed. Researchers have designed cells and built circuits via composition of cells. Some designs have been fabricated and their functionalities and performance verified. This hierarchical approach relies on an abstraction for characterization of cells and composition of cells to design circuits. Researchers have developed such abstractions and methods for characterization of RSFQ cells. However, some instances of cells that are certified as being robust during cell characterization fail when incorporated into circuits. This motivated this research, which we view as the first step in the development of a systematic methodology for verification of cells and circuits in emerging technologies (such as RSFQ) leading to development of more robust abstractions and methods. In this paper, we present a new method for characterization of RSFQ cells to expose a much larger set of vulnerabilities, a systematic approach for identifying the root causes of these vulnerabilities to guide the refinement of cells designs, and a new way to extend test generation approaches to perform design validation at the circuit level. We demonstrate that our new methods and tools expose a large number of vulnerabilities and help identify root causes leading to refined cell designs which almost completely eliminate these vulnerabilities. Finally, we describe our extensions of ATPG for circuit level verification and use it to verify that our refined cells can indeed be composed to create error-free circuits.
机译:RSFQ是基于Josephson结的技术,由于其低能耗和高速度而变得有吸引力。研究人员设计了细胞,并通过细胞组成来构建电路。已经制造出一些设计,并验证了它们的功能和性能。这种分层方法依赖于对单元的表征和单元组成进行设计的抽象。研究人员已经开发出了用于表征RSFQ细胞的抽象和方法。但是,在单元表征期间被证明具有鲁棒性的某些单元实例在并入电路时会失败。这激励了这项研究,我们认为这是开发用于验证新兴技术(例如RSFQ)中的单元和电路的系统方法的第一步,从而开发出更强大的抽象和方法。在本文中,我们提供了一种表征RSFQ细胞以暴露更多漏洞的新方法,一种识别这些漏洞的根本原因的系统方法,以指导细胞设计的完善以及扩展测试生成的新方法在电路级执行设计验证的方法。我们证明了我们的新方法和工具揭示了许多漏洞,并有助于确定导致细化单元设计的根本原因,从而几乎完全消除了这些漏洞。最后,我们描述了用于电路级验证的ATPG扩展,并使用它来验证精制单元的确可以组成无误电路。

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  • 来源
    《International Test Conference》|2019年|1-10|共10页
  • 会议地点 Washington(US)
  • 作者

    Fangzhou Wang; Sandeep Gupta;

  • 作者单位

    University of Southern California Department of Electrical Engineering Los Angeles CA 90089;

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