An Optimized GPS Receiver Architecture for Intellectual Property and System On Chip (SoC) Integration

摘要

The mainstay of GPS receiver architectures in the past has been the stand-alone GPS receiver module, which typically involved an autonomous GPS function integrated with the host system through a serial data bus. More recently with the advent of increasingly low cost and consumer based GPS applications, a chipset based design approach has been used, wherein the GPS solution is integrated with other system functions at the motherboard and subsystem and shares system resources such as CPU, memory, crystal clocks, peripherals, etc. In order to reach even higher levels of system integration and achieve the full benefit of reductions in system size, power consumption, and cost, the most advanced GPS receiver architectures of the future will be realized by the integration of core GPS technology as Intellectual Property (IP) into a larger IP core. This core GPS integration, consisting primarily of the baseband DSP engine, CPU/Memory cells, and embedded software, will provide low cost, location enabled, System On Chip (SOC) capabilities for a wide range GPS applications. This paper will focus on the key technical elements of a GPS IP design, and the hardware design methodology for integrating the GPS IP blocks with standard SoC design processes. The elements of hardware integration include interface requirements with the RF subsystem, DSP integration for weak signal processing, specialized clock and memory segmentations, and a system level approach for software integration. Furthermore, the verification of the GPS IP core requires unique simulation and validation methods, which include propagation of known signal input samples and non-real time processing to verify the GPS IP core at a gate and subsystem level prior to system integration.