Design and Implementation of H.264/SVC Decoder Forecast Module on ASIC

摘要

An ASIC front-end design of intra and inter prediction module based on H.264/SVC standard is proposed in this paper. State machine is used in intra prediction module for timing control. A branch reusable unit ADDR3221 is constructed and optimized to implement the intra prediction in RTL-level. In inter prediction module, the three-level MUX is used to realize the level control from the frame-level to block-level. According to the different segmentation of luma and chroma, the computation of the motion vector and interpolation is realized. Simulation and optimization are performed on the EDA tool of Synopsys platform. Experimental results show that the design of the H.264/SVC forecast module fulfills functional integrity, and the power and the area meet the requirement of design constraint.