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A CMOS merged CDR and Continuous-Time Adaptive Equalizer

机译:CMOS合并CDR和连续时间自适应均衡器

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摘要

We present a low-voltage merged CDR and cntinuous-time adaptive equalizer capable to compensate the attenuation of a SI-POF channel while at the same time synchronizing and regenerating the incoming signal in a single stage. The system operates at 1.25 Gbps for NRZ modulation through a 50-m SI-POF channel and it is designed in standard 0.18-μm CMOS fed at 1 V with a power consumption of 43.4 mW.
机译:我们提出了一种低压合并CDR和连续时间自适应均衡器,该均衡器能够补偿SI-POF通道的衰减,同时在单个阶段同步和再生输入信号。该系统以1.25 Gbps的速度运行,可通过50 m的SI-POF通道进行NRZ调制,并采用标准的0.18μmCMOS设计,电压为1 V,功耗为43.4 mW。

著录项

  • 来源
  • 会议地点 Barcelona(ES)
  • 作者单位

    Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;

    Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;

    Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;

    Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;

    Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Continuous-time linear equalizer; clock and data recovery; low power; low voltage;

    机译:连续时间线性均衡器;时钟和数据恢复;低电量;低电压;
  • 入库时间 2022-08-26 13:49:15

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