Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Group of Electronic Design, Faculty of Science, Universidad de Zaragoza C/ Pedro Cerbuna 12, 50009, Zaragoza, Spain;
Continuous-time linear equalizer; clock and data recovery; low power; low voltage;
机译:基于功率谱估计的CMOS多速率自适应连续时间均衡器设计
机译:用于串行链路的低功耗CMOS 3.3 Gbps连续时间自适应均衡器
机译:具有0.25μmCMOS连续时间宽带延迟线的2.5至3.5Gb / s自适应FIR均衡器
机译:CMOS合并CDR和连续时间自适应均衡器
机译:采用0.13mum CMOS技术的多模光纤通道的自适应模拟均衡。
机译:一个3.0 Gsymbol / S / Lane MIPI C-PHY接收器具有用于移动CMOS图像传感器的自适应电平依赖性均衡器
机译:8.7 A 5Gb / s收发器,具有基于65nm CMOS的基于ADC的前馈CDR和CMA自适应均衡器