Performance analysis of a 4-bit comparator circuit using different adiabatic logics

摘要

In this paper, a 4-bit comparator circuit is designed by using Efficient Charge Recovery Logic (ECRL) and Positive Feedback Adiabatic Logic (PFAL). The designed 4-bit comparator circuit is compared with the conventional CMOS logic in terms of performance parameters like power dissipation and number of transistors used. Simulation results reveal that the 4-bit ECRL comparator is 13.64% more efficient in power consumption as compared to the CMOS comparator, whereas a 4-bit PFAL comparator is 54.54% more efficient in power consumption than the CMOS comparator. All simulations are performed by using cadence virtuoso tool in gpdk 180nm CMOS technology.