Architecture of a FPGA-based Coprocessor: the PAR-1

摘要

The implementation of a FPGA-based coprocessor and its programming methodology are shown. The effects of different sequencing models, and regular and irregular circuits on the hardware and in the programming methodology are discussed. Two examples are described: a sorting network and the kernel of a speech recognition algorithm. The results are still preliminary but they suggest some architectural improvements for general FPGA-based computing machines.