Archit. & Technol. of Comput. Univ. of Seville Seville Spain;
VLSI; delays; field programmable gate arrays; microprocessor chips; FPGA board; VLSI circuit; address-event-representation protocol; asynchronous spike stream; field programmable gate array; multineuron processor; neuromorphic spike-based sensor; time delay; time-warping AER mapper device; visual elementary motion detection model;
机译:空中末端再造商(AER)继续升级设施和过程-AER搬迁到更大的设施并实施多班次以满足需求
机译:Aer,Aqua Et Natura ...旅游与环境的连结:测绘影响
机译:挪威番鸭种子休眠解除过程中ATPase的活性
机译:实施一次扭曲的航值飞机
机译:高性能AER分组网络的FPGA实现。
机译:具有路由和事件排序功能的基于2.8 Gevent / s数据包的AER接口的VLSI实现
机译:时变AER映射器的实现