Tsinghua Nat. Lab. for Inf. Sci. & Technol. Tsinghua Univ. Beijing China;
CMOS integrated circuits; UHF integrated circuits; VHF circuits; delay lock loops; integrated circuit layout; semiconductor process modelling; SMIC CMOS technology; all-digital delay-locked loop; binary search algorithm; dead lock problem; fast locking; frequency 30 MHz to 1 GHz; lock-in cycles; post layout simulation; reversible SAR DLL; reversible successive approximation register; size 0.13 mum;
机译:快速锁定和宽范围11位可逆SAR DLL的实现
机译:宽泛,超快速锁定的全数字SAR DLL,无谐波锁定
机译:适用于DVFS SoC的范围广泛且快速锁定的全数字SARDLL
机译:一个快速锁定和广泛的可逆SAR DLL
机译:SAR快速锁定数字锁相环:使用matlab / simulink进行行为建模和仿真。
机译:可逆PDLLA-PEG-PDLLA共聚物热凝胶的体外合成表征及应用
机译:无谐波锁定的广泛和超快速锁定全数字SAR DLL